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Key Benefits
- PCI-SIG Compliant (multiple entries on the Integrators List)
- Highly (and easily) configurable with the included wizard
- Physical Coding sublayer available
- Endpoint, Root Port, Switch, and Dual-mode configurations
- Delivered with the PLDA Testbench
- Interop-proven with main PHY IPs
- Core proven using different verification IP tools
- Application interface optimized for high throughput and minimized latency
- Free trial includes complete technical support
| Name |
PCI Express XpressRich: ASIC |
| Version |
2.1.0 |
| Description |
The XpressRich IP is an RTL-level IP controller (Verilog and VHDL) that supports all PCIe configurations (root port, endpoint, switch-up, switch-down, and bridge). |
| Function |
PCI Express digital controller including Transaction Layer, Data Link Layer, Physical Layer and Physical Coding Sublayer |
| Target Technologies |
- ASIC .18u (1x lane), .13u and below (x4 Lane and more)
- Structured ASIC and other masked ICs
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| Feature List |
- PCI Express™ Base Specification 1.1 (and 1.0a) compliant
- x1, x4 and x8 Lane configurations
- Supported Designs
- Root Port
- Endpoint
- Shared Silicon Root Port / Endpoint
- Switch (upstream port, downstream port, shared silicon upstream / downstream)
- Bridge
- PIPE
- x1, x4: PIPE 16-bit/125 MHz
- x8: PIPE 8-bit/250 MHz
- PHY interoperability
- Texas Instruments, Rambus, ARM, JMicron,...
- PHY PCS/PMA provided for FPGA prototyping (Altera Stratix GX and Virtex 4 FX)
- NXP PX1012A-EL1 (previously Philips PX1012A-ELI)
- up to 8 Virtual Channels (1 or 2 for Switch designs)
- Configurable Receive and Retry buffers
- Type 0 and Type 1 Configuration spaces
- Up to 6 BARs plus expansion ROM available for Endpoints
- All I/O and Memory windows implemented for Root, Switch and Bridge configurations
- User clock to select custom frequencies
- Configuration Space Backend Access
- Power Management
- All Power States
- Legacy PCI Power Management
- Native Active State Power Management L0s, L1, ...
- Also Supports...
- Multi-Function
- MSI-X
- Multiple MSI generation
- ECRC (End-to-End Cyclic Redundancy Check) generation and forward
- Reduced debug access
- Extended tag
- Advanced Error Reporting (AER)
- ECC protection on Rx buffer
- Extensive test/debug interface accessible to designers
- For switches...Signal propagation: MSI, interrupt, L1/L2 propagation, hotreset
- ASPM L1
- Lane reversal
- Power Down Modes
- Receiver Wakeup Mechanism using Beacon
- Receiver Detect Mechanism
- Electrical Idle State
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PHY Interface
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PIPE 8 bits / 250 MHz
PCS 10 bits / 250 MHz
PIPE 16 bits / 125 MHz
PCS 20 bits / 125 MHz |
| Documentation |
Build History (June 09, 2008)
Getting Started: ASIC (June 09, 2008)
Product Brief: ASIC (May 22, 2007)
Reference Manual (June 09, 2008) |
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